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W6811
SINGLE-CHANNEL VOICEBAND CODEC
(5V Analog, 3V Digital)
Preliminary Data Sheet
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Publication Release Date: October 23, 2003 Revision A10
W6811
1. GENERAL DESCRIPTION
The W6811 is a general-purpose single channel PCM CODEC with pin-selectable -Law or A-Law companding. The device is compliant with the ITU G.712 specification. It operates off of a separated analog (5V) and digital (3V) power supplies and is available in 24-pin PDIP, SOG, SSOP, and TSSOP package options. Functions performed include digitization and reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems. The filters are compliant with ITU G.712 specification. W6811 performance is specified over the industrial temperature range of -40C to +85C. The W6811 includes an on-chip precision voltage reference and an additional power amplifier, capable of driving 300 loads differentially up to a level of 6.3V peak-to-peak. The analog section is fully differential, reducing noise and improving the power supply rejection ratio. The data transfer protocol supports both long-frame and short-frame synchronous communications for PCM applications, and IDL and GCI communications for ISDN applications. W6811 accepts seven master clock rates between 256 kHz and 4.096 MHz, and an on-chip pre-scaler automatically determines the division ratio for the required internal clock.
2. FEATURES
* Power supply: Analog 4.5 - 5.5V Digital 2.7 - 3.3V * * * * * * * * * Typical power dissipation of 25 mW, power-down mode of 0.5 W Fully-differential analog circuit design On-chip precision reference of 1.575 V for a 0 dBm TLP at 600 Push-pull power amplifiers with external gain adjustment with 300 load capability Seven master clock rates of 256 kHz to 4.096 MHz Pin-selectable -Law and A-Law companding (compliant with ITU G.711) CODEC A/D and D/A filtering compliant with ITU G.712 Industrial temperature range (-40C to +85C) Four packages: 24-pin PDIP, SOG, SSOP, and TSSOP
APPLICATIONS
* * * * * * * * * * * Digital Telephone Systems Central Office Equipment Switches, Routers) PABX/SOHO Systems Local Loop card SOHO Routers VoIP Terminals Enterprise Phones ISDN Terminals Analog line cards Digital Voice Recorders (Gateways,
PBX Systems (Gateways, Switches)
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W6811
3. BLOCK DIAGRAM
Receive PCM Interface
BCLKR FSR PCMR BCLKT FST PCMT
Re Int PC cei erf M ve ace Transmit PCM Interface Tra Int ns PC erf mitM ace G.712 CODEC G.711 /A -Law
PAO+ PAOPAI RO AO AI+ AI-
/A-Law V REF V AG
512 kHz 256 kHz MCLK
256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz
Pre -scaler Saler
8 kHz
Voltage reference
Power Conditioning
VDDA
VDDD
VSSA
VSSD
PUI
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Publication Release Date: October 23, 2003 Revision A10
W6811
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION ................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM .............................................................................................................................. 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. FUNCTIONAL DESCRIPTION............................................................................................................ 9 7.1. Transmit Path............................................................................................................................. 9 7.2. Receive Path............................................................................................................................ 10 7.3. Power Management................................................................................................................. 11 7.3.1. Analog Supply ................................................................................................................ 11 7.3.2. Digital Supply ................................................................................................................. 11 7.3.3. Analog Ground Reference Bypass................................................................................. 11 7.3.4. Analog Ground Reference Voltage Output .................................................................... 11 7.4. PCM Interface .......................................................................................................................... 11 7.4.1. Long Frame Sync ........................................................................................................... 12 7.4.2. Short Frame Sync .......................................................................................................... 12 7.4.3. GCI Interface .................................................................................................................. 12 7.4.4. IDL Interface................................................................................................................... 13 7.4.5. System Timing................................................................................................................ 13 8. TIMING DIAGRAMS.......................................................................................................................... 14 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 21 9.1. Absolute Maximum Ratings ................................................................................................... 21 9.2. Operating Conditions ............................................................................................................. 21 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 22 10.1. General Parameters .............................................................................................................. 22 10.2. Analog Signal Level and Gain Parameters............................................................................ 23 10.3. Analog Distortion and Noise Parameters .............................................................................. 24 10.4. Analog Input and Output Amplifier Parameters ..................................................................... 25 10.5. Digital I/O ............................................................................................................................... 27 10.5.1. -Law Encode Decode Characteristics........................................................................ 27 10.5.2. A-Law Encode Decode Characteristics ....................................................................... 28 10.5.3. PCM Codes for Zero and Full Scale ............................................................................ 29 10.5.4. PCM Codes for 0dBm0 Output .................................................................................... 29 11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 30 -4-
W6811
12. PACKAGE SPECIFICATION .......................................................................................................... 32 12.1. 24L TSSOP - 4.4X7.8mm ..................................................................................................... 32 12.2. 24L SOP - 300mil.................................................................................................................. 33 12.3. 24L SSOP - 209mil ............................................................................................................... 34 12.4. 24L PDIP - 300 mil ................................................................................................................ 35 13. ORDERING INFORMATION........................................................................................................... 36 14. VERSION HISTORY ....................................................................................................................... 37
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Publication Release Date: October 23, 2003 Revision A10
W6811
5. PIN CONFIGURATION
VREF RO PAI PAO PAO+ VDDA NC VDDD FSR PCMR PCMI BCLKR PUI
1 VREF 2 RO3 PAI 4 PAO 5 PAO+ 6 VDDA 7 NC 8 VDDD 9 FSR 10 PCMI 11 BCLKR 12 PUI
24 V AG AI+ 23 23 AI 22 AO 21 /A 20 V 19 SSA NC 18 V 17 SSD FSX 16 16 PCMO 15 BCLKT 14 MCLK 13
VAG AI+ AIAO /A-Law VSSA NC VSSD FST PCMT BCLKT MCLK
PDIP/SOP/SSOP/TSSOP
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W6811
6. PIN DESCRIPTION
Pin Name VREF Pin No. 1 VDD* A Functionality This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be decoupled to VSSA through a 0.1 F ceramic decoupling capacitor. No external loads should be tied to this pin. Inverting output of the receive smoothing filter. This pin can typically drive a 2 k load to 1.575 volt peak referenced to the analog ground level. This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage. Inverting power amplifier output. This pin can drive a 300 load to 1.575 volt peak referenced to the VAG voltage level. Non-inverting power amplifier output. This pin can drive a 300 load to 1.575 Volt peak referenced to the VAG voltage level. Analog power supply. This pin should be decoupled to VSSA with a 0.1F ceramic capacitor. Not Connected D Digital power supply. This pin should be decoupled to VSSD with a 0.1F ceramic capacitor. For correct operation, VDDD value should always be lower then VDDA. 8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit and receive are synchronous operations. PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins. PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is selected when this pin is tied to VSSD. The IDL mode is selected when this pin is tied to VDDD. This pin can also be tied to the BCLKT when transmit and receive are synchronous operations. Power up input signal. When this pin is tied to VDDD, the part is powered up. When tied to VSSD, the part is powered down. System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have the MCLK signal synchronous and aligned to the FST signal. This is a requirement in the case of 256 and 512 kHz frequency. PCM transmit bit clock input pin. PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins. 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes. Publication Release Date: October 23, 2003 Revision A10
ROPAI PAOPAO+ VDDA NC VDDD
2 3 4 5 6 7 8
A A A A A
FSR
9
D
PCMR BCLKR
10 11
D D
PUI MCLK
12 13
D D
BCLKT PCMT FST
14 15 16
D D D
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W6811
Pin Name VSSD NC VSSA /A-Law AO AIAI+ VAG Pin No. 17 18 19 20 21 22 23 24 A D A A A A VDD* D Functionality This is the digital supply ground. This pin should be connected to 0V. Not Connected This is the analog supply ground. This pin should be connected to 0V. Compander mode select pin. -Law companding is selected when this pin is tied to VDDD. A-Law companding is selected when this pin is tied to VSSD. Analog output of the first gain stage in the transmit path. Inverting input of the first gain stage in the transmit path. Non-inverting input of the first gain stage in the transmit path. Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal processing. This pin should be decoupled to VSSA with a 0.01F capacitor. This pin becomes high impedance when the chip is powered down.
* These columns represent whether the pin Is driven by Analog (`A') or Digital (`D') power supply.
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W6811
7. FUNCTIONAL DESCRIPTION
W6811 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a complete Law and A-Law compander. The -Law and A-Law companders are designed to comply with the specifications of the ITU-T G.711 recommendation. The block diagram in section 3 shows the main components of the W6811. The chip consists of a PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats. The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample rate with the external frame sync frequency. The power conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. The main CODEC block diagram is shown in section 3.
VA VAG G
+
+
PAO+ PAO PAI
Receive Path
8 D/A Converter w + fC= 3400Hz H Smoot Smoothing n Filter 1 Smoothing Smoot nFilter 2
RO -
/A/ACont Control ol
Transmit Path
AO 8 - /A /A Control Cont A/D Converter ++ fC = 200Hz fC = 200 High Pass H High Filt Filter Pas fC= 3400Hz = Ant-Aliasing H Ant-Aliasi i Filter n Ant-Aliasi Ant-Aliasing Filter AI+ AI -
Figure 7.1 The W6811 Signal Path
7.1. TRANSMIT PATH
The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain setting (see application examples in section 11). The device has an input operational amplifier whose output is the input to the encoder section. If the input amplifier is not required for operation it can be powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The input amplifier can be powered down by connecting the AI+ pin to VDDA or VSSA. The AO pin is selected as an input when AI+ is tied to VDDA and the AI- pin is selected as an input when AI+ is tied to VSSA (see Table 7.1).
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Publication Release Date: October 23, 2003 Revision A10
W6811
AI+ VDDA 1.2 to VDDA-1.2 VSSA
Input Amplifier Powered Down Powered Up Powered Down
Input AO AI+, AIAI-
Table 7.1 Input Amplifier Modes of operation
When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the analog ground voltage VAG. The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is digitized. The signal is converted into a compressed 8-bit digital representation with either -Law or ALaw format. The -Law or A-Law format is pin-selectable through the /A-Law pin. The compression format can be selected according to Table 7.2.
/A-Law Pin VSSA VDDA
Format A-Law -Law
Table 7.2. Pin-selectable Compression Format
The digital 8-bit -Law or A-Law samples are fed to the PCM interface for serial transmission at the sample rate supplied by the external frame sync FST.
7.2. RECEIVE PATH
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed through the pin-selectable -Law or A-Law expander and converted to analog samples. The mode of expansion is selected by the /A-Law pin as shown in Table 7.2. The analog samples are filtered by a low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification. A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is buffered to provide the receive output signal RO-. The RO- output can be externally connected to the PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By using external resistors (see section 11 for examples), various gain settings of this output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting PAI to VDDA. - 10 -
W6811
7.3. POWER MANAGEMENT 7.3.1. Analog Supply
The power supply for the analog part of the W6811 needs to be 5V +/- 10%. This supply voltage is connected to the VDDA pin. The VDDA pin needs to be decoupled to ground through a 0.1 F ceramic capacitor.
7.3.2. Digital Supply
The power supply for the digital part of the W6811 needs to be 3V +/- 10%. This supply voltage is connected to the VDDD pin. The VDDD pin needs to be decoupled to ground through a 0.1 F ceramic capacitor.
7.3.3. Analog Ground Reference Bypass
The system has an internal precision voltage reference which generates the 2.5V mid-supply analog ground voltage. This voltage needs to be decoupled to VSSA at the VREF pin through a 0.1 F ceramic capacitor.
7.3.4. Analog Ground Reference Voltage Output
The analog ground reference voltage is available for external reference at the VAG pin. This voltage needs to be decoupled to VSSA through a 0.01 F ceramic capacitor. The analog ground reference voltage is generated from the voltage on the VREF pin and is also used for the internal signal processing.
7.4. PCM INTERFACE
The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of operation of the interface are shown in Table 7.3. BCLKR 64 kHz MHz VSSD VSSD VDDD VDDD to 4.096 FSR 8 kHz VSSD VDDD VSSD VDDD Interface Mode Long or Short Frame Sync ISDN GCI with active channel B1 ISDN GCI with active channel B2 ISDN IDL with active channel B1 ISDN IDL with active channel B2
Table 7.3 PCM Interface mode selections
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Publication Release Date: October 23, 2003 Revision A10
W6811
7.4.1. Long Frame Sync
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8 kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is held high for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 sec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will become low impedance when the Frame Sync signal FST is high or when the 8 bit data word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes low while the data is transmitted or when half of the LSB is transmitted. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. More detailed timing information can be found in the interface timing section.
7.4.2. Short Frame Sync
The W6811 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is high for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the bit-clock, the W6811 starts clocking out the data on the PCMT pin, which will also change from high to low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway the LSB. The Short Frame Sync operation of the W6811 is based on an 8-bit data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSSD for two or more frame sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK. The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.
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W6811
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to VDDD for two or more frame sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not used for data transmission and also in the time slot of the unused channel. For more timing information, see the timing section.
7.4.5. System Timing
The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz master clock rates. The system clock is supplied through the master clock input MCLK and can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and 8 kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is low for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W6811 will enter the low power standby mode. Another way to power down is to set the PUI pin to low. When the system needs to be powered up again, the PUI pin needs to be set to high and the Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will become low impedance.
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Publication Release Date: October 23, 2003 Revision A10
W6811
8. TIMING DIAGRAMS
T FTR H M T FTR SM TM CK H TM CK L T R ISE T FA LL
M C LK
TM CK T FS T FSL T FTR H T FTR S T FTFH TBCK H TBCK L
FST
B C LK T
0
T FD TD
1
2
3
T B D TD
4
5
6
7
8
T H ID T H ID
0
TBCK
1
PC M T
D7 M SB
D6
D5
D4
D3
D2
D1 D0 LSB
T FS T FSL T FR R H T FR R S T FR FH
FSR
TBCK H
TBCK L
B C LK R
0
1
2
3
4
5
6
7
8
0
TBCK
1
PC M R
D7 M SB
TD RS
D6
D5
TD RH
D4
D3
D2
D1 D0 LSB
Figure 8.1 Long Frame Sync PCM Timing
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W6811
SYMBOL 1/TFS TFSL 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFDTD TBDTD THID
DESCRIPTION FST, FSR Frequency FST / FSR Minimum Low Width BCLKT, BCLKR Frequency BCLKT, BCLKR High Pulse Width BCLKT, BCLKR Low Pulse Width BCLKT 0 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 1 Falling edge Setup Time BCLKT 2 Falling Edge to FST Falling Edge Hold Time FST Rising Edge to Valid PCMT Delay Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the Later of FST Falling Edge, or BCLKT 8 Falling Edge to PCMT Output High Impedance
1
MIN --TBCK 64 50 50 20 80 50 ----10
TYP 8 -------------------
MAX --4096 ----------60 60 60
UNIT kHz sec kHz ns ns ns ns ns ns ns ns
TFRRH TFRRS TFRFH TDRS TDRH
BCLKR 0 Falling Edge to FSR Rising Edge Hold Time FSR Rising Edge to BCLKR 1 Falling edge Setup Time BCLKR 2 Falling Edge to FSR Falling Edge Hold Time Valid PCMR to BCLKR Falling Edge Setup Time PCMR Hold Time from BCLKR Falling Edge
20 80 50 0 50
-----------
-----------
ns ns ns ns ns
Table 8.1 Long Frame Sync PCM Timing Parameters
1
TFSL must be at least TBCK Publication Release Date: October 23, 2003 Revision A10
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W6811
T FTR H M
T FTR SM
TM CK H
TM CK L
T R ISE
T FA LL
M C LK
TM CK T FTFH T FTFS T FS
FST
T FTR H T FTR S TBCK H TBCK L
B C LK T
-1
0
1
T B D TD
2
3
T B D TD
4
5
6
7
8
T H ID
0
TBCK
1
PC M T
D7 M SB
D6
D5
D4
D3
D2
D1 D0 LSB
T FS T FR FH T FR FS
FSR
T FR R H T FR R S TBCK H TBCK L
B C LK R
-1
0
1
2
3
4
5
6
7
8
0
TBCK
1
PC M R
D7 M SB
TD RS
D6
D5
TD RH
D4
D3
D2
D1 D0 LSB
Figure 8.2 Short Frame Sync PCM Timing
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W6811
SYMBOL 1/TFS 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFTFS TBDTD THID TFRRH TFRRS TFRFH TFRFS TDRS TDRH
DESCRIPTION FST, FSR Frequency BCLKT, BCLKR Frequency BCLKT, BCLKR High Pulse Width BCLKT, BCLKR Low Pulse Width BCLKT -1 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 0 Falling edge Setup Time BCLKT 0 Falling Edge to FST Falling Edge Hold Time FST Falling Edge to BCLKT 1 Falling Edge Setup Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from BCLKT 8 Falling Edge to PCMT Output High Impedance BCLKR -1 Falling Edge to FSR Rising Edge Hold Time FSR Rising Edge to BCLKR 0 Falling edge Setup Time BCLKR 0 Falling Edge to FSR Falling Edge Hold Time FSR Falling Edge to BCLKR 1 Falling Edge Setup Time Valid PCMR to BCLKR Falling Edge Setup Time PCMR Hold Time from BCLKR Falling Edge
MIN --64 50 50 20 80 50 50 10 10 20 80 50 50 0 50
TYP 8 -------------------------------
MAX --4096 ------------60 60 -------------
UNIT kHz kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 8.2 Short Frame Sync PCM Timing Parameters
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Publication Release Date: October 23, 2003 Revision A10
W6811
T FS
FST
T FSR H
T FSFH T FSR S 0 1 2 T B D TD 3 4 5 6 TBD TD 7 8 9 T H ID 10 11 12 13 14
TBCK H 15 16
TBCK L 17 18 T H ID D1 D0 LSB
B C LK T
-1
T B D TD
TBD TD
TBCK
PC M T
D7 D6 D5 D4 D3 D2 D1 D0 M SB TD RS TD RH LSB
D7 D6 D5 D4 D3 D2 M SB TD RS TD RH
PC M R
D7 D6 D5 D4 D3 D2 D1 D0 M SB LSB
D7 D6 D5 D4 D3 D2 M SB
D1 D0 LSB
BCH = 0 B 1 C hannel
BCH = 1 B 2 C hannel
Figure 8.3 IDL PCM Timing
SYMBOL 1/TFS 1/TBCK TBCKH TBCKL TFSRH TFSRS TFSFH TBDTD THID
DESCRIPTION FST Frequency BCLKT Frequency BCLKT High Pulse Width BCLKT Low Pulse Width BCLKT -1 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 0 Falling edge Setup Time BCLKT 0 Falling Edge to FST Falling Edge Hold Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the BCLKT 8 Falling Edge (B1 channel) or BCLKT 18 Falling Edge (B2 Channel) to PCMT Output High Impedance Valid PCMR to BCLKT Falling Edge Setup Time PCMR Hold Time from BCLKT Falling Edge
MIN --256 50 50 20 60 20 10 10
TYP 8 -----------------
MAX --4096 ----------60 50
UNIT kHz kHz ns ns ns ns ns ns ns
TDRS TDRH
20 75
-----
-----
ns ns
Table 8.3 IDL PCM Timing Parameters
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W6811
T FS
FST
T FSR H
T FSFH T FSR S
TBCK H
TBCK L
B C LK T
012 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
T FD TD
T B D TD
T H ID
T B D TD
T B D TD T B C K D1 D0 LSB
T H ID
PC M T
D7 D6 D5 D4 D3 D2 D1 D0 M SB TD RS TD RH
D7 D6 D5 D4 D3 D2
LSB M SB TD RS TD RH
PC M R
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 M SB LSB M SB
D1 D0 LSB
BCH = 0 B 1 C hannel
BCH = 1 B 2 C hannel
Figure 8.4 GCI PCM Timing
SYMBOL 1/TFST 1/TBCK TBCKH TBCKL TFSRH TFSRS TFSFH TFDTD TBDTD THID
DESCRIPTION FST Frequency BCLKT Frequency BCLKT High Pulse Width BCLKT Low Pulse Width BCLKT 0 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 1 Falling edge Setup Time BCLKT 1 Falling Edge to FST Falling Edge Hold Time FST Rising Edge to Valid PCMT Delay Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the BCLKT 16 Falling Edge (B1 channel) or BCLKT 32 Falling Edge (B2 Channel) to PCMT Output High Impedance Valid PCMR to BCLKT Rising Edge Setup Time PCMR Hold Time from BCLKT Rising Edge
MIN --512 50 50 20 60 20 ----10
TYP 8 -------------------
MAX --6176 ----------60 60 50
UNIT kHz kHz ns ns ns ns ns ns ns ns
TDRS TDRH
20 ---
-----
--60
ns ns
Table 8.4 GCI PCM Timing Parameters
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Publication Release Date: October 23, 2003 Revision A10
W6811
SYMBOL 1/TMCK
DESCRIPTION Master Clock Frequency
MIN ---
TYP 256 512 1536 1544 2048 2560 4096
MAX ---
UNIT kHz
TMCKH / TMCK TMCKH TMCKL TFTRHM TFTRSM TRISE TFALL
MCLK Duty Cycle for 256 kHz Operation Minimum Pulse Width High for MCLK(512 kHz or Higher) Minimum Pulse Width Low for MCLK (512 kHz or Higher) MCLK falling Edge to FST Rising Edge Hold Time FST Rising Edge to MCLK Falling edge Setup Time Rise Time for All Digital Signals Fall Time for All Digital Signals
45% 50 50 50 50 -----------------
55% --------50 50 ns ns ns ns ns ns
Table 8.5 General PCM Timing Parameters
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W6811
9. ABSOLUTE MAXIMUM RATINGS
9.1. ABSOLUTE MAXIMUM RATINGS Condition
Junction temperature Storage temperature range Voltage Applied to any pin Voltage applied to any pin (Input current limited to +/-20 mA) Lead temperature (soldering VDDA - VSSA ; VDDD - VSSD VDDD - VDDA2 - 10 seconds) Analog Digital Analog Digital 1500C -650C to +1500C (VSSA - 0.3V) to (VDDA + 0.3V) (VSSD - 0.3V) to (VDDD + 0.3V) (VSSA - 1.0V) to (VDDA + 1.0V) (VSSD - 1.0V) to (VDDD + 1.0V) 3000C -0.5V to +6V < 0.3V
Value
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. 2. At any time, the digital power supply should not be higher the 0.3V from the analog power supply.
9.2. OPERATING CONDITIONS Condition
Industrial operating temperature Analog supply voltage (VDDA) Digital supply voltage (VDDD) Ground voltage (VSSA, VSSD)
0
Value
-40 C to +85 C +4.5V to +5.5V +2.7V to +3.3V 0V
0
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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Publication Release Date: October 23, 2003 Revision A10
W6811
10. ELECTRICAL CHARACTERISTICS
10.1. GENERAL PARAMETERS
Symbol VIL VIH VOL VOH IDDA IDDD ISBA ISBD IPDA IPDD IIL IOL CIN COUT VCCA Current (Power Down) VCCD Current (Power Down) Input Leakage Current PCMT Output Leakage Current Digital Input Capacitance PCMT Output Capacitance PCMT High Z VCCA Current (Standby) Parameters Input Low Voltage Input High Voltage PCMT Output Low Voltage PCMT Output High Voltage VDDA Current (Operating) -ADC+DAC IOL = 1.6 mA IOL = -1.6 mA PUI = 1 FSX running MCLK running PUI = 1 FSX = 0 MCLK running PUI = 0 PUI = 0 VSSD1. Typical values: TA = 25C , VDDA = 5.0 V, VDDD = 3.0 V 2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested.
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W6811
10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS
VDDA=5V 10%; VSSA=0V; TA=-40C to +85C; all analog signals referred to VAG; PARAMETER SYM. CONDITION TYP. TRANSMIT (A/D) MIN. Absolute Level Max. Transmit Level Absolute Gain (0 dBm0 @ 1020 Hz; TA=+25C) Absolute Gain variation with Temperature Frequency Response, Relative to 0dBm0 @ 1020 Hz LABS TXMAX GABS 0 dBm0 = 0dBm @ 600 3.17 dBm0 for -Law 3.14 dBm0 for A-Law 0 dBm0 @ 1020 Hz; TA=+25C 1.096 1.579 1.573 0 -------0.25 MAX. ------+0.25 RECEIVE (D/A) MIN. -------0.25 MAX. ------+0.2 5 VPK VPK VPK dB UNIT
GABS
T
TA=0C to TA=+70C TA=-40C to TA=+85C
0
-0.03 -0.05
+0.03 +0.05
-0.03 -0.05
+0.0 3 +0.0 5
dB
GRTV
15 Hz 50 Hz 60 Hz 200 Hz 300 to 3000 Hz 3300 Hz 3400 Hz 3600 Hz 4000 Hz 4600 Hz to 100 kHz
---------------------
-------1.0 -0.20 -0.35 -0.8 -------
-40 -30 -26 -0.4 +0.15 +0.15 0 0 -14 -32
-0.5 -0.5 -0.5 -0.5 -0.20 -0.35 -0.8 -------
0 0 0 0 +0.1 5 +0.1 5 0 0 -14 -30 +0.2 +0.4 +1.6
dB
Gain Variation vs. Level Tone (1020 Hz relative to -10 dBm0)
GLT
+3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0
-------
-0.3 -0.6 -1.6
+0.3 +0.6 +1.6
-0.2 -0.4 -1.6
dB
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Publication Release Date: October 23, 2003 Revision A10
W6811
10.3. ANALOG DISTORTION AND NOISE PARAMETERS
VDDA=5V 10%; VSSA=0V; TA=-40C to +85C; all analog signals referred to VAG;
PARAMETER SYM. CONDITION TRANSMIT (A/D) MIN. Total Distortion vs. Level Tone (1020 Hz, -Law, C-Message Weighted) DLT +3 dBm0 0 dBm0 to -30 dBm0 -40 dBm0 -45 dBm0 Total Distortion vs. Level Tone (1020 Hz, A-Law, Psophometric Weighted) DLTA +3 dBm0 0 dBm0 to -30 dBm0 -40 dBm0 -45 dBm0 Spurious Out-Of-Band at RO- (300 Hz to 3400 Hz @ 0dBm0) Spurious In-Band (700 Hz to 1100 Hz @ 0dBm0) Intermodulation Distortion (300 Hz to 3400 Hz -4 to -21 dBm0 Crosstalk (1020 Hz @ 0dBm0) Absolute Group Delay Group Delay Distortion (relative to group delay @ 1200 Hz) DSPO 4600 Hz to 7600 Hz 7600 Hz to 8400 Hz 8400 Hz to 100000 Hz DSPI 300 to 3000 Hz 36 36 29 25 36 36 29 25 --------TYP. ------------------------MAX . -----------------------47 RECEIVE (D/A) MIN. 34 36 30 25 34 36 30 25 --------TYP. ------------------------MAX. -----------------30 -40 -30 -47 dB dB dBp dBC UNIT
DIM
Two tones
---
---
-41
---
---
-41
dB
DXT ABS D 1200 Hz 500 Hz 600 Hz 1000 Hz 2600 Hz 2800 Hz
-------------------
-------------------
-75 360 750 380 130 130 750 5 -69
-------------------
-------------------
-75 240 750 370 120 120 750 13 -79
dBm0 sec sec
Idle Channel Noise
NIDL
-Law; C-message A-Law; Psophometric
dBrnc dBm0p
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W6811
10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS
VDDA=5V 10%; VSSA=0V; TA=-40C to +85C; all analog signals referred to VAG; PARAMETER AI Input Offset Voltage AI Input Current AI Input Resistance AI Input Capacitance AI Common Mode Input Voltage Range AI Common Mode Rejection Ratio AI Amp Gain Bandwidth Product AI Amp DC Open Loop Gain AI Amp Equivalent Input Noise AO Output Voltage Range Load Resistance Load Capacitance AO & RO Output Current RO- Output Resistance RO- Output Offset Voltage Analog Ground Voltage VAG Output Resistance Power Supply Rejection Ratio (0 to 100 kHz to VDDA, Cmessage) PAI Input Offset Voltage PAI Input Current PAI Input Resistance PAI Amp Gain Bandwidth Product SYM. VOFF,AI IIN,AI RIN,AI CIN,AI VCM,AI CMRRTI GBWTI GTI NTI VTG RLDTGRO CLDTGRO IOUT1 RROVOFF,ROVAG RVAG PSRR CONDITION AI+, AIAI+, AIAI+, AI- to VAG AI+, AIAI+, AIAI+, AIAO, RLD10k AO, RLD10k C-Message Weighted RLD=10k to VAG RLD=2k to VAG AO, RO to VAG AO, RO 0.5 AO,RO- VDDA-0.5 RO-, 0 to 3400 Hz RO- to VAG Relative to VSSA Within 25mV change Transmit Receive VOFF,PAI IIN,PAI RIN,PAI GBWPI PAI PAI PAI to VAG PAO- no load MIN. ----10 --1.2 --------0.5 1.0 2 --1.0 ----2.429 --30 30 ----10 --TYP. --0.1 ------60 2150 95 -24 ----------1 --2.5 2.5 80 75 --0.05 --1000 MAX. 25 1.0 --10 VDDA-1.2 --------VDDA-0.5 VDDA-1.0 --100 ----25 2.573 12.5 ----20 1.0 ----mV A M kHz k pF mA mV V dBC UNIT. mV A M pF V dB kHz dB dBrnC V
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Publication Release Date: October 23, 2003 Revision A10
W6811
PARAMETER Output Offset Voltage Load Resistance Load Capacitance PO Output Current PO Output Resistance PO Differential Gain SYM. VOFF,PO RLDPO CLDPO IOUTPO RPO CONDITION PAO+ to PAOPAO+, PAOdifferentially PAO+, PAOdifferentially 0.5 AO,RO- VDDA-0.5 PAO+ to PAORLD=300, +3dBm0, 1 kHz, PAO+ to PAOZLD=300 ZLD=100nF + 100 ZLD=100nF + 20 PO Power Supply Rejection Ratio (0 to 25 kHz to VDDA, Differential out) MIN. --300 --10.0 ---0.2 TYP. --------1 0 MAX. 50 --1000 ----+0.2 UNIT. mV pF mA dB
GPO
PO Differential Signal to Distortion C-Message weighted
DPO
45 ----40 ---
60 40 40 55 40
-----------
dBC
PSRRPO
0 to 4 kHz 4 to 25 kHz
dB
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W6811
10.5. DIGITAL I/O 10.5.1. -Law Encode Decode Chatacteristics
Normalized Encode Decision Levels Digital Code D7 Sign 8159 7903
:
Normalized D6 Chord 0 D5 Chord 0 D4 Chord 0 D3 Step 0 D2 Step 0 D1 Step 0 D0 Step 0 8031 : 1 0 0 0 1 1 1 1 4191 : 1 0 0 1 1 1 1 1 2079 : 1 0 1 0 1 1 1 1 1023 : 1 0 1 1 1 1 1 1 495 : 1 1 0 0 1 1 1 1 231 : 1 1 0 1 1 1 1 1 99 : 1 1 1 0 1 1 1 1 33 : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 2 0 Decode Levels
1
4319 4063
:
2143 2015
:
1055 991
:
511 479
:
239 223
:
103 95
:
35 31
:
3 1 0
Notes: Sign bit = 0 for negative values, sign bit = 1 for positive values
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Publication Release Date: October 23, 2003 Revision A10
W6811
10.5.2. A-Law Encode Decode Characteristics
Normalized Encode Decision Levels 4096 3968
:
Digital Code D7 Sign D6 Chord D5 Chord D4 Chord D3 Step D2 Step D1 Step D0 Step
Normalized Decode Levels
1
0
1
0
1
0
1
0
4032 :
2048 2048
:
1
0
1
0
0
1
0
1
2112 :
1088 1024
:
1
0
1
1
0
1
0
1
1056 :
544 512
:
1
0
0
0
0
1
0
1
528 :
272 256
:
1
0
0
1
0
1
0
1
264 :
136 128
:
1
1
1
0
0
1
0
1
132 :
68 64
:
1
1
1
0
0
1
0
1
66 :
2 0
1
1
0
1
0
1
0
1
1
Notes: 1. Sign bit = 0 for negative values, sign bit = 1 for positive values 2. Digital code includes inversion of all even number bits
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W6811
10.5.3. PCM Codes for Zero and Full Scale
-Law Level + Full Scale + Zero - Zero - Full Scale Sign bit (D7) 1 1 0 0 Chord bits (D6,D5,D4) 000 111 111 000 Step bits (D3,D2,D1,D0) 0000 1111 1111 0000 Sign bit (D7) 1 1 0 0 A-Law Chord bits (D6,D5,D4) 010 101 101 010 Step bits (D3,D2,D1,D0) 1010 0101 0101 1010
10.5.4. PCM Codes for 0dBm0 Output
-Law Sample 1 2 3 4 5 6 7 8 Sign bit (D7) 0 0 0 0 1 1 1 1 Chord bits (D6,D5,D4) 001 000 000 001 001 000 000 001 Step bits (D3,D2,D1,D0) 1110 1011 1011 1110 1110 1011 1011 1110 Sign bit (D7) 0 0 0 0 1 1 1 1 A-Law Chord bits (D6,D5,D4) 011 010 010 011 011 010 010 011 Step bits (D3,D2,D1,D0) 0100 0001 0001 0100 0100 0001 0001 0100
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Publication Release Date: October 23, 2003 Revision A10
W6811
11. TYPICAL APPLICATION CIRCUIT
0.01 F 0.1 F 27k V AUDIOOUT + 0.1 F 0.1 F 27k 1 V REF 2 RO 3 PAI 4 PAO 5 PAO+ 6 V DDA 7 NC 8 V DDD 9 FSR 10 PCMI PCMR 11 BCLKR Power Control 12 PUI V AG 24 AI+ 23 AI- 22 AO 21 27k 27k V AUDIOIN+ 27k 27k 1.0 F 1.0 F
V AUDIOIN V DDD
V DDA V DDD
/A 20
V SSA 19 NC 18 V SSD 17 FST 16 FSX 16 PCMT 15 PCMO 15 BCLKT 14 MCLK 13
8 kHz PCM OUT 2.048 MHz
PDIP/SOG/SSOP/TSSOP
PCM IN
Figure 11.1 Typical circuit for Differential Analog I/O's
AUDIO OUT RL 2k 0.1F 27k 100F 0.1F 0.1F 27k 1 VREF 2 RO3 PAI 4 PAO5 PAO+ 6 VDDA 7 NC 8 VDDD 9 FSR 10 PCMI PCMR Power Control 12 PUI VAG 24 AI+ 23 AI- 22 AO 21 /A 20 VSSA 19 NC 18 VSSD 17 FST 16 FSX 16 PCMT 15 PCMO 15 MCLK 13
0.01F 27k 27k
27k 27k
AUDIO OUT RL 150 VDDA VDDD
1.0 F 1.0 F VAUDIOIN VDD
8 kHz PCM OUT 2.048 MHz
11 BCLKR BCLKT 14
PDIP/SOG/SSOP/TSSOP
PCM IN
Figure 11.2 Typical circuit for Single Ended Analog I/O's
- 30 -
W6811
1k 0.01 F 0.1 F 27k 1 V REF 2 RO 3 PAI 4 PAO VDDA VDDD 5 PAO+ 0.1 F 0.1 F 6 V DDA 7 NC 8 V DDD 9 FSR 10 PCMI PCMR 11 BCLKR Power Control 27k 12 PUI VAG 24 AI+ 23 AI- 22 AO 21 /A 20 VSSA 19 NC 18 VSSD 17 FST 16 FSX 16 PCMT 15 PCMO 15 BCLKT 14 MCLK 13 100k 100k
200 p F
Electret Microphone WM-54B Panasonic 1.5k
Speake
27k
1k 1k
1.0 F 1.0 F VDD
1.5k
8 kHz PCM OUT 2.048 MHz
PDIP/SOG/SSOP/TSSOP
PCM IN
Figure 11.3 Handset Interface
0.1F
TIP
0.01F 1 VREF VAG 24 AI+ 23 AI- 22 AO 21 /A 20 VSSA 19 NC 18 VSSD 17 FST 16 FSX 16 PCMT 15 PCMO 15 MCLK 13 8 kHz PCM OUT 4.096 MHz 27k 27k 1.0 F VDD
600
600
N= 1 RI NG N= 1
27k
27k
2 RO3 PAI 4 PAO5 PAO+
0.1F VDDD 0.1F
6 VDDA 7 NC 8 VDDD 9 FSR 10 PCMI PCMR
11 BCLKR BCLKT 14 Power Control 12 PUI
PDIP/SOG/SSOP/TSSOP
PCM IN B1 - 0V B2 - +5V
Figure 11.4 Transformer Interface Circuit in GCI mode
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Publication Release Date: October 23, 2003 Revision A10
W6811
12. PACKAGE SPECIFICATION
12.1. 24L TSSOP - 4.4X7.8MM
PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS
DIMENSION IN MM SYMBOL A A1 A2 L E HE D b c L1 e 01 0 4.30 7.70 0.19 0.09 1.0 REF. 0.65 BSC. 8 0 0.05 0.80 0.50 0.90 0.60 6.40 BSC. 4.40 7.80 4.50 7.90 0.30 0.20 0.169 0.303 0.007 0.004 MIN NOM MAX 1.20 0.15 1.05 0.75 0.002 0.031 0.020 MIN
DIMENSION IN INCH NOM MAX 0.043 0.006 0.035 0.024 0.252 BSC. 0.173 0.307 0.177 0.311 0.012 0.008 0.039 REF 0.026 BSC 8 0.041 0.030
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W6811
12.2. 24L SOP-300MIL
SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS
20
11
E
1
10
SEATING PLANE
GAUGE PLANE
DIMENSIONS IN MM SYMBOL A A1 b c E D e HE Y L 0 0.40 0 MIN 2.35 0.10 0.33 0.23 7.40 12.60 10.00 1.27 BSC. 1065 0.10 1.27 8 MAX 2.65 0.30 0.51 0.32 7.60 13.00
DIMENSIONS IN INCH MIN 0.093 0.004 0.013 0.009 0.291 0.946 0.394 0.016 0 MAX 0.104 0.012 0.020 0.013 0.299 0.512 0.419 0.004 0.050 8
0.050 BSC.
- 33 -
Publication Release Date: October 23, 2003 Revision A10
W6811
12.3. 24L SSOP-209 MIL
SHRINK SMALL OUTLINE PACKAGE DIMENSIONS
- 34 -
W6811
12.4. 24L PDIP - 300 MIL
PLASTIC DUAL INLINE PACKAGE
D
24 13
DIMENSIONS
E
1
1
12
S AA L B B1 e1
2
E c A
1
Base Plane Mounting Plane
a
eA
DIMENSION IN MM SYMBOL A A1 A2 B B1 c D E E1 e1 L a eA S 7.37 6.43 2.29 3.05 0 8.38 8.89 0.25 3.18 0.41 1.47 0.20 3.30 0.46 1.52 0.25 31.95 7.62 6.55 2.54 3.30 3.43 0.56 1.63 0.36 32.26 7.87 6.68 2.79 3.56 15 9.40 2.29 0.290 0.253 0.090 0.120 0 0.330 MIN NOM MAX 4.45 0.010 0.125 0.016 0.058 0.008 MIN
DIMENSION IN INCH NOM MAX 0.175 0.130 0.018 0.060 0.010 1.258 0.300 0.258 0.100 0.130 0.350 0.135 0.022 0.064 0.014 1.270 0.310 0.263 0.110 0.140 15 0.370 0.090
- 35 -
Publication Release Date: October 23, 2003 Revision A10
W6811
13. ORDERING INFORMATION
Part Number Description
W6811I _
Package Type:
Product Family
W6811 Product
W S R E
= = = =
24-Lead Plastic Thin Small Outline Package (TSSOP) Type 1 24-Lead Plastic Small Outline Package (SOG/SOP) 24-Lead Plastic Small Outline Package (SSOP) 24-Lead Plastic Dual Inline Package (PDIP)
When ordering W6811 series devices, please refer to the following part numbers.
Part Number
W6811IW W6811IS W6811IR W6811IE
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W6811
14. VERSION HISTORY
VERSION A7 A8 A9 A10 DATE August 9, 2002 Septembe r 26, 2002 October 10, 2002 October 23, 2003 34 Changed the package dimention of the SSOP24 package PAGE Preliminary DESCRIPTION
The information contained in this datasheet may be subject to change without notice. It is the responsibility of the customer to check the Winbond USA website (www.winbond-usa.com) periodically for the latest version of this document, and any Errata Sheets that may be generated between datasheet revisions.
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 http://www.winbond-usa.com/
Winbond Electronics (Shanghai) Ltd.
27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998
Taipei Office
9F, No. 480, Pueiguang Rd. Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd.
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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Publication Release Date: October 23, 2003 Revision A10

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